The Open Verification Methodology (OVM) is an open-source SystemVerilog class library and advanced methodology that defines a framework for reusable verification IP (VIP) and tests. It is based on the IEEE 1800 SystemVerilog standard and provides building blocks (objects) and a common set of verification-related utilities. The OVM release is under the Apache 2.0 license, enabling anyone to use OVM libraries for any purpose, including creation of derivative work.
, the OVM facilitates true SystemVerilog interoperability with a standard library and a proven methodology. It combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is tested on two-thirds of the industry’s SystemVerilog simulators. The OVM also facilitates the development and usage of plug-and-play VIP written in SystemVerilog, SystemC®, and e languages.
Features/Benefits
Delivers an open, unified class library and methodology for interoperable VIP
Base for the forthcoming Accellera Universal Verification Methodology (UVM) standard
Integrates with the proven Incisive Plan-to-Closure Methodology
Provides built-in automation and testbench capabilities
Supports module-to-system and project-to-project reuse
