Development Tools / System-RF IC Design-

Description
Document

Cadence® Virtuoso® Spectre® Circuit Simulator provides fast, accurate SPICE-level simulation for tough analog, radio frequency (RF) and mixed-signal circuits. It is tightly integrated with the Virtuoso custom design platform and provides detailed transistor-level analysis in multiple domains. Its superior architecture allows for low memory consumption and high-capacity analysis.

Features/Benefits

Provides high-performance, high-capacity SPICE-level analog and RF simulation with out-of-the-box tuning for accuracy and convergence
Facilitates the tradeoff between accuracy and performance through user-friendly simulation setup applicable to the most complex analog and custom-digital ICs
Enables accurate and efficient post-layout simulation with RLCK parasitics, S-Parameter models (n-port), and lossy coupled transmission lines (mtline)
Performs application-specific analysis of RF performance parameters (spectral response, gain compression, inter-modulation distortion, impedance matching, stability, isolation)
Includes advanced statistical analysis (Smart, MonteCarlo, DCmatch) to help design companies improve the manufacturability and yield of ICs at advanced process nodes without sacrificing time to market
Delivers fast interactive simulation set-up, cross-probing, visualization, and post-processing of simulation results through tight integration with Virtuoso Analog Design Environment
Ensures higher design quality using silicon-accurate, foundry-certified device models shared within Virtuoso Multi-Mode Simulation

文档(Document)

Virtuoso Spectre Circuit Simulator

Features/Benefits

文档(Document)

PRODUCTS

SOLUTIONS

NEWS

ABOUT US

No.	PDF	Description
1	Accelerating Analog Simulation with Full Spice Accuracy White Paper	Accelerating Analog Simulation with Full Spice Accuracy White Paper
2	Assura Geometry Extraction and Spectre Re-simulation Flow to Simulate Shallow Trench Isolation (STI)	Assura Geometry Extraction and Spectre Re-simulation Flow to Simulate Shallow Trench Isolation (STI) Stress Effects in Analogue Circuits
3	Cadence and IBM SOI Success Story	Cadence and IBM SOI Success Story
4	Cadence and Multigig Success Story	Cadence and Multigig Success Story
5	Cadence and Teradyne Success Story	Cadence and Teradyne Success Story
6	Cadence and TowerJazz Success Story	Cadence and TowerJazz Success Story
7	Cadence Space-Based Router, the next generation	Cadence Space-Based Router, the next generation
8	Cadence Virtuoso Custom Design Platform Brochure	Cadence Virtuoso Custom Design Platform Brochure
9	Detecting and Managing Device Reliability in Block-level and Chip-level Simulations	Detecting and Managing Device Reliability in Block-level and Chip-level Simulations
10	Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators	Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators
11	Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element	Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element
12	IBM z-Series Microprocessor and Cache Subsystem Chips Use CSR to Drive Multi-Gigahertz Design Point	IBM z-Series Microprocessor and Cache Subsystem Chips Use CSR to Drive Multi-Gigahertz Design Point
13	RF Analysis in Virtuoso Spectre Circuit Simulator XL Datasheet	RF Analysis in Virtuoso Spectre Circuit Simulator XL Datasheet
14	Use of the Incremental Technology Database for Design in IC 6.1 and OA 2.2	Use of the Incremental Technology Database for Design in IC 6.1 and OA 2.2
15	Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer	Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer
16	Virtuoso Multi-Mode Simulation Datasheet	Virtuoso Multi-Mode Simulation Datasheet