A high-performance, high-density complex programmable logic device (CPLD) with Atmel's proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, the device easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. Enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The device has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected individually within each macrocell.
