Cadence Chip Optimizer

品牌:Cadence
描述:使用基于3D空间的方法进行建模、分析并优化版图,使其满足电气约束,制造规则等等。
包装:
封装:
无铅情况/ROHS: 有铅
类别:数字实现
经营商:科通芯城自营

文档(Document)

序号 PDF 描述
1 Cadence Chip Optimizer Datasheet     Cadence Chip Optimizer Datasheet
2 Cadence Space-Based Router, the next generation     Cadence Space-Based Router, the next generation
3 Performance Impact from Metal Fill Insertion     Performance Impact from Metal Fill Insertion
4 Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure     Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure
5 Virtuoso Custom Design Demo: High-performance Custom Routing and DFM Optimization for Advanced Proce     Virtuoso Custom Design Demo: High-performance Custom Routing and DFM Optimization for Advanced Process Nodes using the Cadence Space-based Router and Chip Optimizer

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