Encounter Conformal Equivalence Checker

品牌:Cadence
描述:Handles large, complex datapaths, digital custom logic, custom memories, and FPGA designs—from RTL t
包装:
封装:
无铅情况/ROHS: 有铅
类别:逻辑设计
经营商:科通芯城自营


Already proven in thousands of tapeouts, Encounter Conformal EC is the industry’s most widely supported independent equivalence checking product. It is production-proven on more physical design closure products, advanced synthesis software, ASIC libraries, and IP cores than any other formal verification technology.

Benefits
  • Exhaustively verifies multi-million–gate ASICs and FPGAs several times faster than traditional gate-level simulation
  • Decreases the risk of missing critical bugs with independent verification technology
  • Enables faster, more accurate bug detection and correction throughout the entire design flow
  • Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout verification gap (XL configuration)
  • Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)

文档(Document)

序号 PDF 描述
1 Cadence and NetEffect Success Story     Cadence and NetEffect Success Story
2 Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design     Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design
3 Cadence Encounter Digital IC Design Platform Brochure     Cadence Encounter Digital IC Design Platform Brochure
4 Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow     Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow
5 Encounter Conformal Equivalence Checker Datasheet     Encounter Conformal Equivalence Checker Datasheet
6 Functional ECO with Conformal Technology     Functional ECO with Conformal Technology
7 Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs     Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs
8 Static Verification for Design Reuse and Quality     Static Verification for Design Reuse and Quality

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