Incisive Design Team Manager

品牌:Cadence
描述:Drives verification closure using incrementally developed assertion and test list plans. Captures an
包装:
封装:
无铅情况/ROHS: 有铅
类别:功能验证
经营商:科通芯城自营

文档(Document)

序号 PDF 描述
1 Beyond the Compliance Checklist     Beyond the Compliance Checklist
2 Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodol     Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
3 Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approa     Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach
4 Cadence Low-Power Solution Demo     Cadence Low-Power Solution Demo
5 Coverage-Driven Verification for Mixed-Signal Systems     Coverage-Driven Verification for Mixed-Signal Systems
6 Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf     Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
7 Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project     Do's and Dont's for Systematically Implementing Late Engineering Changes on Your Project
8 Implementing an Automated Checking Scheme for a Video-Processing Device     Implementing an Automated Checking Scheme for a Video-Processing Device
9 Integrating Design IP and Verification IP to Ensure Quality and Predictability     Integrating Design IP and Verification IP to Ensure Quality and Predictability
10 Interview: By Popular Demand—SystemVerilog Open Verification Methodology     Interview: By Popular Demand—SystemVerilog Open Verification Methodology
11 Interview: Verification Planning and Management Methodology Focuses on All the Right Things     Interview: Verification Planning and Management Methodology Focuses on All the Right Things
12 Leveraging Assertions in System Verilog Testbench to get to Closure     Leveraging Assertions in System Verilog Testbench to get to Closure
13 Methods to Improve Verification Quality on the Module Level     Methods to Improve Verification Quality on the Module Level
14 Methods to Improve Verification Quality on the Module Level     Methods to Improve Verification Quality on the Module Level
15 Packaging Reusable Components, EZ-start Guide     Packaging Reusable Components, EZ-start Guide
16 Power-Aware Verification Spans IC Design Cycle White Paper     Power-Aware Verification Spans IC Design Cycle White Paper
17 Practical Guide to Low-Power Design - User Experience with CPF     Practical Guide to Low-Power Design - User Experience with CPF
18 Speed up and prove verification by using a generic scoreboard library     Speed up and prove verification by using a generic scoreboard library
19 Test Sequence Reuse from Block to System with the Incisive Plan-to-Closure Methodology     Test Sequence Reuse from Block to System with the Incisive Plan-to-Closure Methodology
20 Working with Interfaces, EZ-start Guide     Working with Interfaces, EZ-start Guide

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