Incisive Design Team Simulator

品牌:Cadence
描述:Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (co
包装:
封装:
无铅情况/ROHS: 有铅
类别:逻辑设计
经营商:科通芯城自营


Cadence® Incisive® Design Team Simulator provides testbench creation, reuse, and analysis capabilities to verify designs from the system level, through RTL, to the gate level. The environment supports a coverage-driven methodology from verification planning to closure. Incisive Design Team Simulator’s native-compiled architecture speeds the simultaneous simulation of behavioral, transaction (TLM), RTL, and gate-level models, eliminating the performance degradation in traditional co-simulation. It also supports industry-standard verification languages and is compatible with the Open Verification Methodology (OVM, so engineers can quickly and easily integrate Incisive Design Team Simulator with established verification flows.

Features/Benefits
  • Supports testbench generation, analysis, and reuse
  • Offers comprehensive coverage capabilities including code, functional, and transactional
  • Provides HDL analysis capabilities
  • Drives and guides verification with an automatically backannotated and executable verification plan
  • Automates the transfer of coverage data to verification management products
  • Supports SystemC®, SystemVerilog, Verilog®, VHDL , PSL, and SVA

文档(Document)

序号 PDF 描述
1 Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodol     Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
2 Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approa     Building Transaction-Based Acceleration Regression Environment using Plan-Driven Verification Approach
3 Cadence Low-Power Solution Demo     Cadence Low-Power Solution Demo
4 Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf     Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
5 Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog     Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog
6 Functional Closure using the Plan-to-Closure Methodology     Functional Closure using the Plan-to-Closure Methodology
7 Implementing an Automated Checking Scheme for a Video-Processing Device     Implementing an Automated Checking Scheme for a Video-Processing Device
8 Integrating Design IP and Verification IP to Ensure Quality and Enhance Productivity     Integrating Design IP and Verification IP to Ensure Quality and Enhance Productivity
9 Integrating Design IP and Verification IP to Ensure Quality and Predictability     Integrating Design IP and Verification IP to Ensure Quality and Predictability
10 Interview: By Popular Demand—SystemVerilog Open Verification Methodology     Interview: By Popular Demand—SystemVerilog Open Verification Methodology
11 Interview: Verification Planning and Management Methodology Focuses on All the Right Things     Interview: Verification Planning and Management Methodology Focuses on All the Right Things
12 Methods to Improve Verification Quality on the Module Level     Methods to Improve Verification Quality on the Module Level
13 Metric-Driven Verification Ensures Software Development Quality White Paper     Metric-Driven Verification Ensures Software Development Quality White Paper
14 Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog     Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
15 Packaging Reusable Components, EZ-start Guide     Packaging Reusable Components, EZ-start Guide
16 Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodol     Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodology
17 Practical Guide to Low-Power Design - User Experience with CPF     Practical Guide to Low-Power Design - User Experience with CPF
18 SystemC Simulation in the Cadence Design Environment for Protocols and Networks Verification and Est     SystemC Simulation in the Cadence Design Environment for Protocols and Networks Verification and Estimation
19 Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology     Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology
20 Working with Interfaces, EZ-start Guide     Working with Interfaces, EZ-start Guide

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