Virtuoso AMS Designer

品牌:Cadence
描述:Provides an advanced mixed-signal simulation solution for design and verification of analog, RF, mem
包装:
封装:
无铅情况/ROHS: 有铅
类别:定制IC设计
经营商:科通芯城自营


Cadence® Virtuoso® AMS Designer is a mixed-signal simulation solution for the design and verification of analog, RF, memory, and mixed-signal SoCs. It is integrated with the Virtuoso full-custom environment for mixed-signal design and verification. It is also integrated with the Cadence Incisive® functional verification platform for mixed-signal verification within the digital verification environment.

Features/Benefits
  • Ensures design quality with proven Virtuoso analog and Incisive digital simulation technologies
  • Supports both analog design flow use model in Virtuoso Analog Design Environment as well as digital verification use model in Incisive Environment
  • Supports top-down methodology to quickly detect design failures early in the design cycle to make sure the design is ready for tape-out, right on time
  • Accelerates simulation with mixed-signal hardware description language support
  • Accelerates simulation of RF circuits at full SPICE accuracy by combining envelope analysis of RF transceivers with digital baseband simulation

文档(Document)

序号 PDF 描述
1 A Top Down Design Methodology for Mixed-signal Integrated Circuits using the VppSim Simulator     A Top Down Design Methodology for Mixed-signal Integrated Circuits using the VppSim Simulator
2 Accelerating Analog Simulation with Full Spice Accuracy White Paper     Accelerating Analog Simulation with Full Spice Accuracy White Paper
3 AMS Designer Migration, Usability, and Performance Improvements     AMS Designer Migration, Usability, and Performance Improvements
4 Assura Design Rule Checker Datasheet     Assura Design Rule Checker Datasheet
5 Cadence and LSI Corporation Success Story     Cadence and LSI Corporation Success Story
6 Cadence and Texas Instruments Success Story     Cadence and Texas Instruments Success Story
7 Cadence and TowerJazz Success Story     Cadence and TowerJazz Success Story
8 Cadence Virtuoso Custom Design Platform Brochure     Cadence Virtuoso Custom Design Platform Brochure
9 Co-simulation: Virtuoso AMS Simulators and Simulink (Mathworks) on Real Designs     Co-simulation: Virtuoso AMS Simulators and Simulink (Mathworks) on Real Designs
10 Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element     Full-Chip Mixed-Signal Verification Using High Precision Digital-Analog Interface Element
11 Full-Chip Verification Flow with Third-Party IP Using AMS Methodology     Full-Chip Verification Flow with Third-Party IP Using AMS Methodology
12 Getting Plastered Article     Getting Plastered Article
13 Mixed Signal Verification Methodology Using AMS-Ultra     Mixed Signal Verification Methodology Using AMS-Ultra
14 Mixed-Signal Assertion Based Verification     Mixed-Signal Assertion Based Verification
15 Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation     Speed Up RF Mixed-Signal Simulation Using Novel Hierarchical Fast Envelope Simulation
16 Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer     Virtuoso Custom Design Demo: Solving D/MS Design Challenges with Virtuoso AMS Designer
17 Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release)     Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release)
18 Virtuoso Multi-Mode Simulation Datasheet     Virtuoso Multi-Mode Simulation Datasheet

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