Virtuoso Analog Design Environment

品牌:Cadence
描述:Provides a comprehensive array of capabilities for electrical and statistical analysis, verification
包装:
封装:
无铅情况/ROHS: 有铅
经营商:科通芯城自营


Designed to help users create manufacturing-robust designs, Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses. By supporting extensive exploration of multiple designs against their objective specifications, Virtuoso Analog Design Environment sets the standard in fast and accurate design verification.

Features/Benefits
  • Reduced learning curve with a simulator-independent environment
  • Maximum efficiency in the script-driven mode
  • Accelerated debug process using a variety of built-in analog analysis tools
  • Facilitated design correction via easy comparison of pre- and post-parasitic extracted designs
  • Quick detection of circuit problems via a clear visualization cockpit

文档(Document)

序号 PDF 描述
1 Cadence and Fuji Electric Success Story     Cadence and Fuji Electric Success Story
2 Cadence and LSI Corporation Success Story     Cadence and LSI Corporation Success Story
3 Cadence and Realtek Success Story     Cadence and Realtek Success Story
4 Cadence and Teradyne Success Story     Cadence and Teradyne Success Story
5 Cadence and TowerJazz Success Story     Cadence and TowerJazz Success Story
6 Getting Plastered Article     Getting Plastered Article
7 Migration to Virtuoso IC61 Based on OpenAccess (OA)     Migration to Virtuoso IC61 Based on OpenAccess (OA)
8 Schematic Debugging Framework for Multi-Simulator-Based Verification of Mixed-Signal Designs     Schematic Debugging Framework for Multi-Simulator-Based Verification of Mixed-Signal Designs
9 Virtuoso Analog Design Environment Family Datasheet     Virtuoso Analog Design Environment Family Datasheet
10 Virtuoso Analog Design Environment GXL Datasheet     Virtuoso Analog Design Environment GXL Datasheet
11 Virtuoso Analog Design Environment L Datasheet     Virtuoso Analog Design Environment L Datasheet
12 Virtuoso Analog Design Environment XL Datasheet     Virtuoso Analog Design Environment XL Datasheet
13 Virtuoso Analog ElectronStorm Option Datasheet     Virtuoso Analog ElectronStorm Option Datasheet
14 Virtuoso Analog VoltageStorm Option Datasheet     Virtuoso Analog VoltageStorm Option Datasheet
15 Virtuoso Chip Assembly Router Datasheet     Virtuoso Chip Assembly Router Datasheet
16 Virtuoso Chip Editor Datasheet     Virtuoso Chip Editor Datasheet
17 Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release)     Virtuoso Custom Design Demo: Virtuoso Constraint Flow (IC 6.1 release)
18 Virtuoso Custom Design Platform XL Datasheet     Virtuoso Custom Design Platform XL Datasheet
19 Virtuoso Digital Implementation Datasheet     Virtuoso Digital Implementation Datasheet
20 Virtuoso Specification-driven Environment Datasheet     Virtuoso Specification-driven Environment Datasheet

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