W971GG6JB

品牌:Winbond
描述:The W971GG6JB is a 1G bits DDR2 SDRAM, and speed involving -18, -25, 25L, 25I, 25A, 25K?and -3.
包装:
封装:WBGA 84 Ball (8x12.5mm2), using Lead free materials with RoHS compliant
无铅情况/ROHS: 无铅
经营商:科通芯城自营
参数 数值
Voltage 1.8/1.8V
Voltage 1.8V±0.1V
Package WBGA 84 Ball (8x12.5mm2), using Lead free materials with RoHS compliant
Package WBGA-84
Status P
Density 1Gb
CL-tRCD-tRP 5-5-5
CL-tRCD-tRP 6-6-6
Organization 64Mbit x16
Organization 64Mbitx16/8 Banks
RoHS Y
Speed Grade 533MHz//-18
Speed Grade DDR2-1066//-18
Speed Grade DDR2-667//-3
Speed Grade DDR2-800//-25/25I/25L/25A/25K
Density 1Gb
Organization 64Mbit x16
Voltage 1.8/1.8V
Speed —18/533MHz
Package WBGA-84
Status P
RoHS Y
Description
The W971GG6JB is a 1G bits DDR2 SDRAM, and speed involving -18, -25, 25L, 25I, 25A, 25K?and -3. Status: Mass Production
Features
Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V Double Data Rate architecture: two data transfers per clock cycle CAS Latency: 3, 4, 5, 6 and 7 Burst Length: 4 and 8 Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data Edge-aligned with Read data and center-aligned with Write data DLL aligns DQ and DQS transitions with clock Differential clock inputs (CLK and /CLK) Data masks (DM) for write data Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS Posted /CAS programmable additive latency supported to make command and data bus efficiency Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality Auto-precharge operation for read and write bursts Auto Refresh and Self Refresh modes Precharged Power Down and Active Power Down Write Data Mask Write Latency = Read Latency - 1 (WL = RL - 1) Interface: SSTL_18

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