Allegro PCB SI

品牌:Cadence
描述:Provides advanced interconnect modeling for constraint development and electrical analysis of multi-
包装:
封装:
无铅情况/ROHS: 有铅
类别:Allegro PCB
经营商:科通芯城自营


Integrated with Cadence® Allegro® PCB design, editing, and routing technologies, Allegro PCB SI provides advanced signal integrity (SI) analysis both pre- and post-layout. Operating early in the design cycle allows for “what-if” scenario exploration, sets more accurate design constraints, and reduces design iterations.

Allegro PCB SI reads and writes directly to the Allegro PCB Editor database for fast and accurate integration of results. It provides a SPICE-based simulator and an embedded field solver, and it supports behavioral modeling with a robust modeling language. Bus architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals. The Allegro PCB Power Delivery Network (PDN) Analysis Option provides modeling of all power distribution characteristics.

Features/Benefits
  • Performs a wide variety of SI analyses
  • Reduces design errors to increase first-pass success
  • Sets accurate constraints, quickly and early in the process
  • Improves product performance through solution-space exploration
  • Explores alternative topologies in the earliest stages
  • Supports modeling and testing for multi-gigahertz signals
  • Generates S-Parameters from signal topologies
  • Generates estimated crosstalk tables to increase design efficiency
  • Performs post-layout verifications directly from Allegro PCB Editor
  • Enables device model creation, modification, and verification
  • Verifies multiple-board and silicon-package-board signal paths
  • Analyzes power distribution system characteristics

文档(Document)

序号 PDF 描述
1 2008 CDNLive MVP Case Study - New Technologies for 6 Gbps Serial Link Design and Simulation     2008 CDNLive MVP Case Study - New Technologies for 6 Gbps Serial Link Design and Simulation
2 2008 CDNLive MVP Case Study Presentation - New Technologies for 6 Gbps Serial Link Design and Simula     2008 CDNLive MVP Case Study Presentation - New Technologies for 6 Gbps Serial Link Design and Simulation
3 2009 DesignCon Case Study - New Serial Link Simulation Process, 6 Gbps SAS     2009 DesignCon Case Study - New Serial Link Simulation Process, 6 Gbps SAS
4 2010 DesignCon Paper Award Finalist - Simulation Techniques for 6+ Gbps Serial Links     2010 DesignCon Paper Award Finalist - Simulation Techniques for 6+ Gbps Serial Links
5 3D S-Parameter Simulation in Allegro SI     3D S-Parameter Simulation in Allegro SI
6 A Process for Serial Link Signal Integrity Analysis - XrossTalk Magazine Article     A Process for Serial Link Signal Integrity Analysis - XrossTalk Magazine Article
7 Allegro PCB Power Delivery Network Analysis Datasheet     Allegro PCB Power Delivery Network Analysis Datasheet
8 Automating FPGA-Based PC Board Designs     Automating FPGA-Based PC Board Designs
9 Cadence OrCAD PCB SI Datasheet     Cadence OrCAD PCB SI Datasheet
10 Cadence PCB Signal and Power Integrity Datasheet     Cadence PCB Signal and Power Integrity Datasheet
11 Cadence Signal Integrity for Double Data Rate Interface     Cadence Signal Integrity for Double Data Rate Interface
12 Cadence Signal Integrity for Double Data Rate Interface     Cadence Signal Integrity for Double Data Rate Interface
13 How to Overcome Challenges in Designing a DDR2/DDR3 Memory System     How to Overcome Challenges in Designing a DDR2/DDR3 Memory System
14 Interview: Signals on Serial Links: Now you see ‘em, now you don’t. What can we do?     Interview: Signals on Serial Links: Now you see ‘em, now you don’t. What can we do?
15 IR-Drop Analysis White Paper     IR-Drop Analysis White Paper
16 Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2     Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2
17 Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI     Modeling Analog Circuits with Routed Interconnect using AMS and Allegro SI
18 Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Links Work Right Out of the Box     Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Links Work Right Out of the Box
19 Using mm.pl to Create DML MacroModels for Use in Channel Analysis     Using mm.pl to Create DML MacroModels for Use in Channel Analysis
20 Xilinx RocketIO Design Kit     Xilinx RocketIO Design Kit

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